Oscillator circuits are used in determining timing of events in electronic circuits. Oscillator circuits have been used in determining timing in which to de-assert a reset signal, for example. Oscillator circuits also have been used in watchdog timeout circuits in determining timing in which to reset a counter on a device input, for example.
A supervisory circuit is commonly used to monitor one or more parameters of devices such as power supplies and microprocessors which must be maintained within certain limits, and to take appropriate action if a parameter goes out of bounds, creating an unacceptable or dangerous situation, for example. Supervisory circuits have been used during a power up sequence to delay active usage of a device until system power has come up to a correct level and stabilized. For example, when supply voltage of a device such as a microprocessor has just returned back to its normal operating voltage level after being in a low voltage supply state (i.e. brown-out state), or after emerging from a ‘hung’ state, a supervisory circuit may delay active usage of the microprocessor until after its supply voltage has been within a normal operating range for at least a predefined time out period.
In particular, for example, supervisory circuits have been used to de-assert one or more reset signals to place a device into an active usage state. In the past, some supervisory circuits have included timer circuitry to determine duration of a predefined reset time out interval that occurs prior to de-assertion of one or more reset signals used to place a device into the active usage state. Some prior supervisory circuits have provided variable reset timeout intervals. Some prior timers have provided reset timeout intervals that are externally-tunable via an off-chip component, rather than being already fixed and pre-defined on-chip. External tenability can provide the flexibility to use the same supervisor circuit and its component timer in different kinds of applications with varying reset timeout period requirements.
FIG. 1 is an illustrative schematic diagram showing a prior timer circuit 100 that includes a tunable capacitor (Cext) 102 to provide a tunable reset timeout period. The tunable capacitor 102 ordinarily is provided as a programmable off-chip (external) capacitor. The timer works by charging and discharging the external capacitor 102 between two voltage levels Vref1 and Vref2.
The timer circuit 100 includes first and second comparator circuits 106, 108 coupled to compare a capacitor voltage VC of the tunable capacitor 102 with each of a first reference voltage Vref1 and a second reference voltage Vref2. The comparator circuits 106, 108 are further coupled to provide first and second comparison voltage signals V1, V2 that transition in state in response to charging and discharging, respectively, of the capacitor 102 voltage VC. In other words, a value of the first comparison signal V1 transitions in response to the capacitor 102 charging, and a value of the second comparison signal V2 transitions in response to the capacitor 102 discharging. A latch circuit 110 is coupled to produce an output voltage VL having a value indicative of the most recently transitioned comparison voltage signal V1 or V2. In other words, between occurrences of transitions of the first and second comparison signals, the latch circuit 110 stores a value that is indicative of the most recently provided one of the first and second comparison voltage signals. That is, the latch circuit 110 stores a value indicative of which switch state the switch 114 currently is in at times while the capacitor voltage is between the two reference levels, Vref1 and Vref2.
The timer circuit 100 includes logic circuitry 112 and a switch 114. The logic circuitry 112 is coupled to receive the VL signal, which is fed back from the latch 110, and to also receive an Enable signal. In response to the Enable signal enabling the logic circuitry 112, the logic circuitry provides as its output a VI signal that acts as an input to the switch 114.
The switch 114 includes a PMOS device 116 and an NMOS device 118 having their drains coupled together so that the PMOS device 116 acts as a voltage pull-up device and the NMOS device acts as a voltage pull-down device. A first current source 120 is coupled to provide current I to a source of the PMOS device 116. A second current sink 122 is coupled to sink a current I from a source of the NMOS device 118. The drains of the PMOS device 116 and the NMOS device 118 are coupled to a switch output terminal 124 that is coupled to a first terminal of the tunable capacitor 102. A second terminal of the tunable capacitor 102 is coupled to ground.
The timer circuit 100 includes a counter circuit 126 that is coupled to receive as input the VL signal produced by the latch. The counter circuit 126 operates to count occurrences of rising (or falling) edges of the VL signal. The counter circuit 126 provides a timeout signal (TO) in response occurrence of m VL rising edges. Thus, the timer circuit 100 delays provision of a timeout signal until a count of VL rising edges reaches m. The timeout signal can be used by a supervisor circuit to determine when to de-assert a reset signal, for example.
In operation, when the Enable signal is high (that is, when the timer 100 is enabled) the two comparators 106, 108 sense when VC has reached one of the voltage thresholds, Vref1 or Vref2, and in response to determining that a threshold has been reached, produce a signal V1 or V2 that transitions the latch 110 to a different state. The output VL of the latch 110 feeds back to the input logic circuit 112, which controls the switch 114 to alternately turn on the pull-up PMOS device 116 or to turn on the NMOS pull-down device 118, to alternately switch in and out the current sources 120, 122, to alternately charge and discharge the capacitor 102. Meanwhile, the output of latch 110 is digitally divided by the counter 126 by a certain divide ratio m to generate the timeout signal TO after the occurrences of m transitions of the VL signal. The occurrence of the TO signal indicates that the reset timeout interval has elapsed.
With the capacitor charging and discharging currents I, the comparator thresholds Vref1 and Vref2, and the counter divide ratio m all fixed on-chip, varying the external capacitance Cext effectively changes the charge and discharge rate of the capacitor, thus realizing a variable oscillator frequency and thus, a tunable timeout period.
Neglecting the comparator offset and propagation delay, it can be derived that the time-out period of for the prior timer circuit of FIG. 1 can be represented as,
  Timeout  =                    2        ⁢                  mC          ext                    I        ⁢                  (                              Vref            ⁢                                                  ⁢            1                    -                      Vref            ⁢                                                  ⁢            2                          )            .      
From this equation, it can be seen that the time-out period is directly proportional to Cext. The time-out period is also a function of the current I, the divide ratio m, and the difference between the pre-defined comparator thresholds, A capacitor as the variable external device, as in the circuit in FIG. 1 can readily achieve a time-out period range of up to four orders of magnitude using a suitable range of commercially-available external capacitor values.
Using off-chip capacitors, however, can have some disadvantages. For example, some external capacitors have a poor absolute value, as well as both temperature and voltage coefficient, thereby degrading the time-out accuracy. Moreover, the time-out period is also heavily dependent on the accuracy of the on-chip bias currents I.